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[Other Embeded program] verilogpll

Description: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Platform: | Size: 3072 | Author: letheo | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[Wavelet] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93184 | Author: li | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[DSP program] PLL

Description: 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
Platform: | Size: 6144 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Platform: | Size: 18432 | Author: gjj | Hits:

[Other] pll_funcnl

Description: pll in verilog in the Appendix
Platform: | Size: 227328 | Author: jadedfox | Hits:

[Industry research] pll_verilog

Description: verilog model of a P-verilog model of a PLL
Platform: | Size: 135168 | Author: jadedfox | Hits:

[VHDL-FPGA-Verilog] pll

Description: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Platform: | Size: 734208 | Author: prescaler | Hits:

[Communication-Mobile] EP2C8_pll_example

Description: EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.-EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
Platform: | Size: 485376 | Author: tupeng | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Platform: | Size: 384000 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
Platform: | Size: 216064 | Author: ad | Hits:

[Software Engineering] PLL(pdf)

Description: 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
Platform: | Size: 73728 | Author: 李强 | Hits:

[VHDL-FPGA-Verilog] verilog_PLL

Description: verilog 写的硬件 pll 锁相环实现-verilog to pll
Platform: | Size: 409600 | Author: 王亮 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: Phase locked loop(PLL) Verilog HDL code
Platform: | Size: 20480 | Author: hr | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
Platform: | Size: 1024 | Author: louxy | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function
Platform: | Size: 3072 | Author: Henin Lu | Hits:

[VHDL-FPGA-Verilog] my_uart1_VERILOG_using-PLL

Description: Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using PLL
Platform: | Size: 506880 | Author: 林端 | Hits:

[VHDL-FPGA-Verilog] verilog-pll

Description: 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
Platform: | Size: 1323008 | Author: loadziliao | Hits:
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